Exploiting Parallelism for Faster Implementation of Bubble Sort Algorithm Using FPGA

被引：0

作者：

Lipu, Ashrak Rahman ^{[1
]}

Amin, Ruhul ^{[1
]}

Mondal, Md. Nazrul Islam ^{[1
]}

Al Mamun, Md. ^{[1
]}

机构：

[1] RUET, Dept Comp Sci & Engn, Rajshahi, Bangladesh

来源：

2016 2ND INTERNATIONAL CONFERENCE ON ELECTRICAL, COMPUTER & TELECOMMUNICATION ENGINEERING (ICECTE) | 2016年

关键词：

FPGA; Bubble Sort; Clock Cycle; Odd-even transposition; Swappers; Schematic view;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Sorting is a classic problem that has been studied for decades. From the beginning of computing, many Sorting algorithms have been investigated. Bubble sort is a very common and powerful sorting technique used in different applications. For high speed data processing, we need faster and efficient environment for any sorting algorithm. In this purpose, FPGA based hardware accelerators can show better performance for high speed data processing than the general purpose processors. In this paper, the sequential and parallel bubble sort algorithm is implemented using FPGA. We show that parallel implementation of Bubble sort algorithm is almost 10 times faster than that of sequential implementation for 20 different data inputs. However, this implementation is faster for more data inputs.

引用

页数：4

共 8 条

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[7] Shin D, 2009, IEEE INT SYMP CIRC S, P1, DOI 10.1109/ISCAS.2009.5117670
[8] Srivastava Ajitesh, 2015, 2015 International Conference on Reconfigurable Computing and FPGAs (ReConFig), P1, DOI 10.1109/ReConFig.2015.7393322

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