Design and simulation of a novel 1400V-4000V enhancement mode buried gate GaN HEMT for power applications

A novel enhancement mode structure, a buried gate gallium nitride (GaN) high electron mobility transistor (HEMT) with a breakdown voltage (BV) of 1400 V-4000 V for a source-to-drain spacing (L-SD) of 6 mu m-32 mu m, is investigated using simulations by Silvaco Atlas. The simulations are based on meticulous calibration of a conventional lateral 1 i.tm gate length GaN HEMT with a source-to-drain spacing of 6 mu m against its experimental transfer characteristics and BV. The specific on-resistance R-S for the new power transistor with the source-to-drain spacing of 6 mu m showing BV = 1400 V and the source-to-drain spacing of 8 mu m showing BV = 1800 V is found to be 2.3 m Omega.cm(2) and 3.5 m Omega.cm(2), respectively. Further improvement up to BV = 4000 V can be achieved by increasing the source-to-drain spacing to 32 mu m with the specific on-resistance of R-S = 35.5 m Omega.cm(2). The leakage current in the proposed devices stays in the range of similar to 5 x 10(-9) mA mm(-1).