Fault-Tolerant Systolic Array Based Accelerators for Deep Neural Network Execution

被引：60
作者：
Zhang, Jeff [1 ]
Basu, Kanad [1 ]
Garg, Siddharth [1 ]
机构：
[1] NYU, Dept Elect & Comp Engn, New York, NY USA
来源：
IEEE DESIGN & TEST | 2019年 / 36卷 / 05期
基金：
美国国家科学基金会;
关键词：
Fault tolerance; Fault tolerant systems; Neural networks; Computer architecture; Clocks; Google; Fault Toerance; Reliability; Testing; Systolic Arrays; Deep Neural Networks;
D O I：
10.1109/MDAT.2019.2915656
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Editor's note: Systolic array is embracing its renaissance after being accepted by Google TPU as the core computing architecture of machine learning acceleration. In this article, the authors propose two strategies to enhance fault tolerance of systolic array based deep neural network accelerators. - Yiran Chen, Duke University. © 2013 IEEE.
引用
收藏
页码：44 / 53
页数：10
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