Low Cost Design of an Advanced Encryption Standard (AES) Processor Using a New Common-Subexpression-Elimination Algorithm

被引：1

作者：

Chen, Ming-Chih ^{[1
]}

Hsiao, Shen-Fu ^{[2
]}

机构：

[1] Natl Kaohsiung First Univ Sci & Technol, Dept Elect Engn, Kaohsiung, Taiwan

[2] Natl Sun Yat Sen Univ, Dept Comp & Informat Eng, Kaohsiung, Taiwan

来源：

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | 2009年 / E92A卷 / 12期

关键词：

AES; VLSI; common subexpression elimination (CSE); information security; logic synthesis; ARCHITECTURES;

D O I：

10.1587/transfun.E92.A.3221

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper. we propose an area-efficient design of Advanced Encryption Standard (AES) processor by applying a new common-expression-elimination (CSE) method to the sub-functions of various transformations required in AES. The proposed method reduces the area cost of realizing the sub-functions by extracting the common factors in the bit-level XOR/AND-based sum-of-product expressions of these sub-functions using a new CSE algorithm. Cell-based implementation results show that the AES processor with our proposed CSE method has significant area improvement compared with previous designs.

引用

页码：3221 / 3228

页数：8