Design and evaluation of a novel real-shared cache module for high performance parallel processor chip
被引:0
作者:
Liu, Z
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机构:
Tohoku Univ, Dept Bioengn & Robot, Aoba Ku, Sendai, Miyagi 9808579, JapanTohoku Univ, Dept Bioengn & Robot, Aoba Ku, Sendai, Miyagi 9808579, Japan
Liu, Z
[1
]
Shim, J
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机构:
Tohoku Univ, Dept Bioengn & Robot, Aoba Ku, Sendai, Miyagi 9808579, JapanTohoku Univ, Dept Bioengn & Robot, Aoba Ku, Sendai, Miyagi 9808579, Japan
Shim, J
[1
]
Kurino, H
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机构:
Tohoku Univ, Dept Bioengn & Robot, Aoba Ku, Sendai, Miyagi 9808579, JapanTohoku Univ, Dept Bioengn & Robot, Aoba Ku, Sendai, Miyagi 9808579, Japan
Kurino, H
[1
]
Koyanagi, M
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Tohoku Univ, Dept Bioengn & Robot, Aoba Ku, Sendai, Miyagi 9808579, JapanTohoku Univ, Dept Bioengn & Robot, Aoba Ku, Sendai, Miyagi 9808579, Japan
Koyanagi, M
[1
]
机构:
[1] Tohoku Univ, Dept Bioengn & Robot, Aoba Ku, Sendai, Miyagi 9808579, Japan
来源:
PARALLEL AND DISTRIBUTED COMPUTING: APPLICATIONS AND TECHNOLOGIES, PROCEEDINGS
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2004年
/
3320卷
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D O I:
暂无
中图分类号:
TP301 [理论、方法];
学科分类号:
081202 ;
摘要:
Nowadays, it is very important that integrating parallel processors on a chip offers high performance and low interactive response time on applications with fine-grained parallelism and high degree of data sharing. We propose a novel real-shared cache module with new multiport ring-bus architecture to overcome the bus bottleneck problem of the existing parallel processors chip on shared cache level. A testbench of solving a large scale of simultaneous linear equation is also designed to evaluate such architecture. The evaluation results show that it can offer immediate data sharing without conflicts or delay, and the performance of parallel processors chips with such novel real-shared cache module improves in proportion to the number of processor elements.