Architecture Design of a Comparator for SAR ADC

被引:0
|
作者
Xiu Limei [1 ]
Li Zheying [1 ]
机构
[1] Beijing Union Univ, Inst Microelect Applicat Tech, Beijing 100101, Peoples R China
来源
ISTM/2009: 8TH INTERNATIONAL SYMPOSIUM ON TEST AND MEASUREMENT, VOLS 1-6 | 2009年
关键词
High-precision; low power dissipation; Switched Operational Amplifier; 1-V;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A novel high-speed and high-precision voltage comparator has been proposed. In the comparator design, the Switched Operational Amplifier technique is adopted in the pre-amplifier stage to reduce the power consumption. The proposed voltage comparator is designed for 1MHz 12-bit SAR ADC under TSMC 180nm 1P6M CMOS technology. The resolution of the voltage comparator is 0.2mV under the 1.8V power supply with the sample rate of 20MS/s.
引用
收藏
页码:3166 / 3169
页数:4
相关论文
共 50 条
  • [41] An Improved Dynamic Latch Based Comparator for 8-bit Asynchronous SAR ADC
    Bekal, Anush
    Joshi, Rohit
    Goswami, Manish
    Singh, Babu. R.
    Srivatsava, Ashok
    2015 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, 2015, : 178 - 182
  • [42] Comparator noise extraction and compensation technique for accuracy enhancement in 16 bit SAR ADC
    Zhang, Panpan
    Feng, Wenjiang
    Zhao, Peng
    Song, Yang
    IEICE ELECTRONICS EXPRESS, 2024, 21 (02):
  • [43] Modified SR Latch in Dynamic Comparator for Ultra-low Power SAR ADC
    Sharuddin, Iffa
    Lee, L.
    2015 IEEE INTERNATIONAL CIRCUITS AND SYSTEMS SYMPOSIUM (ICSYS), 2015, : 151 - 154
  • [44] A Comparator-Reused Dynamic-Amplifier for Noise-Shaping SAR ADC
    Luo, Longheng
    Shen, Xingchen
    Diao, Jianguo
    Ye, Fan
    Ren, Junyan
    2019 IEEE 13TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2019,
  • [45] Design and Analysis of a Power-Efficient Dynamic Comparator with an Improved Transconductance in Ultra-low Power SAR ADC Applications
    Moghadam, Zahra Mehrabi
    Salehi, Mohammad Reza
    Nashta, Salman Roudgar
    Abiri, Ebrahim
    CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2024, 43 (12) : 7498 - 7520
  • [46] Design of Low Power, High Speed, Low Offset and Area Efficient Dynamic-Latch Comparator for SAR-ADC
    Bandla, Kasi
    Harikrishnan, A.
    Pal, Dipankar
    PROCEEDINGS OF 2020 INTERNATIONAL CONFERENCE ON INNOVATIVE TRENDS IN COMMUNICATION AND COMPUTER ENGINEERING (ITCE), 2020, : 299 - 302
  • [47] Low Power Design of Asynchronous SAR ADC
    Ashraf, Ayash
    Ashraf, Shazia
    Rizvi, Navaid Zafar
    Dar, Shakeel Ahmad
    2016 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, AND OPTIMIZATION TECHNIQUES (ICEEOT), 2016, : 4214 - 4219
  • [48] Digital Calibration Technique for Subrange ADC Based on SAR Architecture
    Ju, Ying
    Li, Fule
    Gu, Xian
    Zhang, Chun
    Wang, Zhihua
    2016 5TH INTERNATIONAL SYMPOSIUM ON NEXT-GENERATION ELECTRONICS (ISNE), 2016,
  • [49] A Nonuniform Quantization Scheme for High Speed SAR ADC Architecture
    Kim, Youngchun
    Guo, Wenjuan
    Tewfik, Ahmed H.
    2017 25TH EUROPEAN SIGNAL PROCESSING CONFERENCE (EUSIPCO), 2017, : 991 - 995
  • [50] Analysis and Modeling of a SAR-VCO Hybrid ADC Architecture
    Liang, Yuhua
    Zhu, Zhangming
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2018, 27 (03)