Architecture Design of a Comparator for SAR ADC

被引：0
|
作者：
Xiu Limei [1 ]
Li Zheying [1 ]
机构：
[1] Beijing Union Univ, Inst Microelect Applicat Tech, Beijing 100101, Peoples R China
来源：
ISTM/2009: 8TH INTERNATIONAL SYMPOSIUM ON TEST AND MEASUREMENT, VOLS 1-6 | 2009年
关键词：
High-precision; low power dissipation; Switched Operational Amplifier; 1-V;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A novel high-speed and high-precision voltage comparator has been proposed. In the comparator design, the Switched Operational Amplifier technique is adopted in the pre-amplifier stage to reduce the power consumption. The proposed voltage comparator is designed for 1MHz 12-bit SAR ADC under TSMC 180nm 1P6M CMOS technology. The resolution of the voltage comparator is 0.2mV under the 1.8V power supply with the sample rate of 20MS/s.
引用
收藏
页码：3166 / 3169
页数：4
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