A High Speed Low Power Pipelined SAR Analog to Digital Converter

By combining the advantages of the high speed and high resolution pipelined ADC and the low power SAR ADC, the two stages pipelined SAR ADC is proposed. It mainly reduces the power hungry operation amplifier by removing the front-end sample-and-hold circuit of the capacitor array in SAR ADCs and the sampling switch. Hence, the whole circuit only requires one operational amplifier which is used in the MDAC circuit. The capacitor arrays used in the SAR ADC adopt the monotonic switching procedure to achieve a better energy efficiency and a higher operation speed. An additional comparator for the MSB of the proposed ADC is designed for the ADC using in the sample phasing. It can enhance the sampling rate and can relax the design difficulty of the operation amplifier in the MDAC. The simulated results show that the proposed pipelined SAR ADC can be operated at 80MS/s with 11.17 ENOB and is implemented in TSMC 0.18um process and 1.8V supply voltage.