Novel 3-D Coaxial Interconnect System for Use in System-in-Package Applications

被引:9
|
作者
LaMeres, Brock J. [1 ]
McIntosh, Christopher [1 ]
Abusultan, Monther [1 ]
机构
[1] Montana State Univ, Dept Elect & Comp Engn, HSDDL, Bozeman, MT 59717 USA
来源
IEEE TRANSACTIONS ON ADVANCED PACKAGING | 2010年 / 33卷 / 01期
关键词
Integrated circuit (IC) packaging; simultaneous switching noise (SSN); system-in-package (SiP); three-dimensional (3-D) chip stacking; IMPEDANCE; DESIGN;
D O I
10.1109/TADVP.2009.2033942
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
This paper presents the design and demonstration of a novel die-to-die interconnect system for deployment in system-in-package (SiP) applications with adjacent or stacked-die configurations. The interconnect system consists of miniature coaxial cables that are mounted to a standard Silicon substrate using an etched trench along the perimeter of the die. The trench serves as a self-alignment feature for both the signal and ground contacts in addition to providing mechanical strain relief for the coaxial cable. The system is designed to interface on-chip coplanar transmission lines to off-chip coaxial transmission lines to produce a fully impedance matched system. This approach promises to dramatically improve the electrical performance of high-speed, die-to-die signals by eliminating impedance discontinuities, providing a shielded signal path, and providing a low-impedance return path for the switching signal. The new interconnect system is designed to be selectively added to a standard wire bond pad configuration using an incremental etching process. This paper describes the design process for the new approach including the fabrication sequence to create the transition trenches. Finite-element analysis is performed to evaluate the electrical performance of the proposed system.
引用
收藏
页码:37 / 47
页数:11
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