On Model Order Reduction of Interconnect Circuit Network: A Fast and Accurate Method

被引:1
|
作者
Wang, Xinsheng [1 ]
Fan, Shimin [1 ]
Dai, Ming-Zhe [2 ]
Zhang, Chengxi [3 ]
机构
[1] Harbin Inst Technol Weihai, Weihai 264200, Peoples R China
[2] Cent South Univ, Sch Aeronaut & Astronaut, Changsha 410083, Peoples R China
[3] Harbin Inst Technol, Sch Elect & Informat Engn, Shenzhen 518055, Peoples R China
基金
中国国家自然科学基金;
关键词
model reduction; state variable analysis method; square error; LINEAR-NETWORKS; SYSTEMS;
D O I
10.3390/math9111248
中图分类号
O1 [数学];
学科分类号
0701 ; 070101 ;
摘要
The time cost in integrated circuit simulation is an important consideration in the design. This paper investigates the model order reduction of interconnect circuit networks to facilitate numerical analysis. A novel fast and accurate time reduced order model is proposed to simplify the interconnection network structure analysis and perform a fast simulation. The novelty of this study is the use of the power function sum to extend the approximate function to replace the original system's state function. We give several simulations to verify the effectiveness of the algorithm. The innovation of this model is due to its use of the approximate function of power series expansion to replace the state function of the original system.
引用
收藏
页数:13
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