共 50 条
- [41] 32nm node technology development using interference immersion lithography Advances in Resist Technology and Processing XXII, Pt 1 and 2, 2005, 5753 : 491 - 501
- [42] The optimization of low power operation SRAM circuit for 32nm node SISPAD 2007: SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES 2007, 2007, : 397 - 400
- [43] Lithography and yield sensitivity analysis of SPAM scaling for the 32nm node DESIGN FOR MANUFACTURABILITY THROUGH DESIGN-PROCESS INTEGRATION, 2007, 6521
- [44] Double patterning design split implementation and validation for the 32nm node DESIGN FOR MANUFACTURABILITY THROUGH DESIGN-PROCESS INTEGRATION, 2007, 6521
- [45] Holistic feedforward control for the 5 nm node and beyond OPTICAL MICROLITHOGRAPHY XXXII, 2019, 10961
- [46] Backscattered Electron Imaging for Embedded Subtle Defects in 32nm Processes ISTFA 2010: CONFERENCE PROCEEDINGS FROM THE 36TH INTERNATIONAL SYMPOSIUM FOR TESTING AND FAILURE ANALYSIS, 2010, : 108 - +
- [47] Pattern density and process related CD corrections at 32nm node PHOTOMASK TECHNOLOGY 2007, PTS 1-3, 2007, 6730
- [48] Accelerating 32nm BEOL technology development by advanced wafer inspection methodology LITHOGRAPHY ASIA 2008, 2008, 7140
- [50] Process options for improving electromigration performance in 32nm technology and beyond 2009 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, VOLS 1 AND 2, 2009, : 832 - +