Analysis and Design of Fully Integrated High-Power Parallel-Circuit Class-E CMOS Power Amplifiers

被引：31

作者：

Lee, Ockgoo ^{[1
]}

An, Kyu Hwan ^{[1
]}

Kim, Hyungwook ^{[1
]}

Lee, Dong Ho ^{[1
]}

Han, Jeonghu ^{[1
]}

Yang, Ki Seok ^{[2
]}

Lee, Chang-Ho ^{[2
]}

Kim, Haksun ^{[2
]}

Laskar, Joy ^{[1
]}

机构：

[1] Georgia Inst Technol, Sch Elect & Comp Engn, Georgia Elect Design Ctr, Atlanta, GA 30308 USA

[2] Samsung Design Ctr, Atlanta, GA 30308 USA

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2010年 / 57卷 / 03期

关键词：

Breakdown; CMOS power amplifier (PA); parallel-circuit class-E PA; parallel combining; power loss; transformer; DISTRIBUTED ACTIVE-TRANSFORMER; FEED INDUCTANCE; RF; EFFICIENCY; COMBINER; LOSSES; PAE;

D O I：

10.1109/TCSI.2009.2023944

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A design methodology for watt-level, fully integrated CMOS power amplifiers (PAs) is presented. It is based on the analysis of the operation and power loss mechanism of class-E PAs, which includes the effects of a finite dc-feed inductance and an impedance matching transformer. Using the proposed approach, a class-E PA with a 2 x 1:2 step-up on-chip transformer was implemented in a 0.18-mu m CMOS technology. With a 3.3 V supply, the fully integrated PA achieves an output power of 2 W and a power-added efficiency of 31% at 1.8 GHz.

引用

页码：725 / 734

页数：10

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