Minimizing phase noise variation in CMOS ring oscillators

The variation of phase noise across the frequency of operation of a CMOS ring oscillator is described analytically. The delay element of the ring oscillator considered comprises of a source-coupled differential pair with an active load element. In this circuit topology where the frequency of oscillation is varied by changing the resistance of the load, theory derived in this work predicts that phase noise will remain constant if constant output swing is maintained. Such an oscillator is designed in a 0.5 mum CMOS process and the simulation results verify the theoretical analysis. Consequently, an oscillator design methodology is provided that dramatically reduces the phase noise optimization problem to just one frequency within the oscillator's output frequency range.