A V-Band 40 nm CMOS Phase Locked Loop with Mutual Injection Locking Technique

被引：0

作者：

Zhou, Qian ^{[1
]}

Han, Yan ^{[1
]}

Zhang, Shifeng ^{[1
]}

Han, Xiaoxia ^{[1
]}

Jie, Lu ^{[1
]}

Cheung, Ray C. C. ^{[2
]}

Feng, Guangtao ^{[3
]}

机构：

[1] Zhejiang Univ, Inst Microelect & Photoelect, Hangzhou 310027, Peoples R China

[2] City Univ Hong Kong, Dept Elect Engn, Hong Kong 999077, Peoples R China

[3] Semicond Mfg Int Corp, Shanghai 201203, Peoples R China

来源：

2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT) | 2016年

关键词：

FREQUENCY-SYNTHESIZER; GHZ; PLL;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a V-band phase-locked loop (PLL) that employs zero blind zone phase frequency detector (PFD) and mutual injection-locking voltage controlled oscillator (VCO) to improve signal quality performance. This architecture is fabricated in 40-nm CMOS process with a die area of 0.7 mm(2). The silicon results demonstrate an excellent in-band phase noise of -90 dBc/Hz at 500 kHz offset with 2.5 MHz bandwidth. The PLL draws 40.8 mA current (including output buffer) from a 1.2 V power supply while operating at 60.8 GHz.

引用

页码：539 / 541

页数：3

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