Hardware event-driven simulation engine for spiking neural networks

被引:10
作者
Agis, R. [1 ]
Ros, E. [1 ]
Diaz, J. [1 ]
Carrillo, R. [1 ]
Ortigosa, E. M. [1 ]
机构
[1] Univ Granada, Dept Architecture & Comp Technol, E-18071 Granada, Spain
关键词
event-driven; pipelined datapath; FPGA device; SNN computing engines;
D O I
10.1080/00207210701308625
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The efficient simulation of spiking neural networks (SNN) remains an open challenge. Current SNN computing engines are still far away from simulating systems of millions of neurons efficiently. This contribution describes a computing scheme that takes full advantage of the massive parallel processing resources available at FPGA devices. The computing engine adopts an event-driven simulation scheme and an efficient next-event-to-go searching method to achieve high performance. We have designed a pipelined datapath, in order to compute several events in parallel avoiding idle computing resources. The system is able to compute approximately 2.5 million spikes per second. The whole computing machine is composed only of an FPGA device and five external memory SRAM chips. Therefore, the presented approach is of high interest for simulation experiments that require embedded simulation engines (for instance, in robotic experiments with autonomous agents).
引用
收藏
页码:469 / 480
页数:12
相关论文
共 16 条
[1]  
Boucheny C, 2005, LECT NOTES COMPUT SC, V3512, P136
[2]   ORGANIZATION OF SEMICONDUCTOR MEMORIES FOR PARALLEL-PIPELINED PROCESSORS [J].
BRIGGS, FA ;
DAVIDSON, ES .
IEEE TRANSACTIONS ON COMPUTERS, 1977, 26 (02) :162-169
[3]   SpikeNET: A simulator for modeling large networks of integrate and fire neurons [J].
Delorme, A ;
Gautrais, J ;
van Rullen, R ;
Thorpe, S .
NEUROCOMPUTING, 1999, 26-7 :989-996
[4]   SpikeNET: an event-driven simulation package for modelling large networks of spiking neurons [J].
Delorme, A ;
Thorpe, SJ .
NETWORK-COMPUTATION IN NEURAL SYSTEMS, 2003, 14 (04) :613-627
[5]  
ECKHORN R, 1989, P ICNN, V1, P723
[6]  
Glackin B, 2005, LECT NOTES COMPUT SC, V3512, P552
[7]   An FPGA-based approach to high-speed simulation of conductance-based neuron models [J].
Graas, EL ;
Brown, EA ;
Lee, RH .
NEUROINFORMATICS, 2004, 2 (04) :417-435
[8]  
JAHNKE A, 1997, LECT NOTES COMPUTER, V1327, P1187
[9]   A discrete-event neural network simulator for general neuron models [J].
Makino, T .
NEURAL COMPUTING & APPLICATIONS, 2003, 11 (3-4) :210-223
[10]   Efficient event-driven simulation of large networks of spiking neurons and dynamical synapses [J].
Mattia, M ;
Del Giudice, P .
NEURAL COMPUTATION, 2000, 12 (10) :2305-2329