Comparative Analysis and Design of Harmonic Aware Low-Power Latches and Flip-Flops

This paper develops a methodology to analyze and suppress higher order switching harmonics in high frequency digital CMOS circuits. The spectrum of output signal yields the amount of harmonic content present in switching waveforms. Transistor model quality and input signal influence the harmonic content. We provide the comparative analysis among Flip flops and Latches topologies simulated on 1 GHZ frequency using both BSIM3v3 and BSIM4 transistor models. It is implied that more steeper the spectrum roll-off the lesser the contents of higher order harmonics. Furthermore, the results of comparison show significant improvement in spectrum roll-off with BSIM4 models for all topologies. Among all topologies hybrid latch flip flop comes out to be a best design with much steeper roll-off up to 130dB/decade on 65nm process node.