Open-Source RISC-V Processor IP Cores for FPGAs - Overview and Evaluation

被引:0
作者
Hoeller, Roland [1 ]
Haselberger, Dominic [1 ]
Ballek, Dominik [1 ]
Roessler, Peter [1 ]
Krapfenbauer, Markus [2 ]
Linauer, Martin [2 ]
机构
[1] Univ Appl Sci Technikum Wien, Dept Elect Engn, Hochstadtpl 6, A-1200 Vienna, Austria
[2] Kapsch TrafficCom AG, Europl 2, A-1120 Vienna, Austria
来源
2019 8TH MEDITERRANEAN CONFERENCE ON EMBEDDED COMPUTING (MECO) | 2019年
关键词
Field Programmable Gate Arrays; Programmable System-on-Chip; Open-Source CPU Cores; RISC-V; IP Core;
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Advances in semiconductor miniaturization are an important driver for Field Programmable Gate Arrays (FPGAs) since their invention in the 1980s. The increasing number of available on chip logic resources on one hand and on the other hand a decrease in part costs let the FPGA market grow steadily in recent years. It comes thus at no surprise that more and more microprocessors are integrated into programmable logic devices as they represent the central functionality in many digital systems. In parallel to these technological developments the open-source hardware community grew steadily in the last two decades. More than hundred open-source CPU cores can thus be found and selecting a core for a design project has to be done with care. In this work we thus want to focus on open-source 32-bit CPU IP cores suitable for FPGAs and which support the upcoming free and open RISC-V instruction set architecture that has some interesting advantages when compared to commercial CPU cores (as will be outlined in the paper). An overview on available projects and activities will be given and evaluation results for a selection of cores will be presented.
引用
收藏
页码:122 / 127
页数:6
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