A high performance MQ encoder architecture in JPEG2000

被引：26

作者：

Liu, Kai ^{[1
]}

Zhou, Yu ^{[2
]}

Li, Yun Song ^{[2
]}

Ma, Jian Feng ^{[1
]}

机构：

[1] Xidian Univ, Sch Comp Sci & Technol, Xian 710071, Peoples R China

[2] Xidian Univ, Natl Key Lab Integrated Serv Networks, Xian 710071, Peoples R China

来源：

INTEGRATION-THE VLSI JOURNAL | 2010年 / 43卷 / 03期

基金：

中国国家自然科学基金;

关键词：

MQ encoder; Process elements;

D O I：

10.1016/j.vlsi.2010.01.001

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a novel architecture for an MQ arithmetic coder with high throughput is proposed. The architecture can process two symbols in parallel. The main characteristics are eight process elements for the prediction of probability interval A, the combination of calculation units for the code register C with the Byteout&Flush procedure, and the use of a dedicated probability estimation table to decrease the internal memory. From FPGA synthesis results, the architecture's throughput can reach 96.60 M context symbols per second with an internal memory size of 1509 bits, which is comparable to that of other architectures and suitable for chip implementation. (C) 2010 Elsevier B.V. All rights reserved.

引用

页码：305 / 317

页数：13

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