A CMOS 50% duty cycle repeater using complementary phase blending

被引：29

作者：

Nakamura, K ^{[1
]}

Fukaishi, M ^{[1
]}

Hirota, Y ^{[1
]}

Nakazawa, Y ^{[1
]}

Yotsuyanagi, M ^{[1
]}

机构：

[1] NEC Corp Ltd, Kanagawa 2291198, Japan

来源：

2000 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2000年

关键词：

D O I：

10.1109/VLSIC.2000.852847

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Reported here is a duty cycle repeater (DCR) which obtains 50% duty-cycle complementary clock signals from a wide range of input duty-cycle signals from 30% to 70%, even when input signals suffer from timing skew. It features a simple CMOS structure, with a newly developed complementary phase blending architecture and a symmetrical phase blending inverter.

引用

页码：48 / 49

页数：2