Effect of 2nd gate insulator thickness on the performance of a-Si:H thin-film transistor on plastic substrate

We fabricated a conventional BCE (back channel etched) hydrogenated amorphous silicon thin-film transistor with double layers of gate insulator, BCB (benzocyclobutene) and SiNx, on PES (polyethersulfone) substrate at the maximum deposition temperature of 150 degreesC. We used BCB as the 1(st) gate insulator to reduce the internal stress induced by the difference of the CTE (coefficient of thermal expansion). The thickness of BCB (1(st) gate insulator) was fixed, and then SiNx was varied from 400 nm to 50 nm. The threshold voltage of the TFT decreases from 2 V to 0.3 V with decreasing thickness. The mechanical strain and threshold-voltage shift are also greatly reduced by decreasing the SiNx thickness.