Performance and reliability of sub-100nm TaSiN metal gate fully-depleted SOI devices with high-K (HfO2) gate dielectric

被引：0

作者：

Thean, AVY ^{[1
]}

Vandooren, A ^{[1
]}

Kalpat, S ^{[1
]}

Du, Y ^{[1
]}

To, I ^{[1
]}

Hughes, J ^{[1
]}

Stephens, T ^{[1
]}

Goolsby, B ^{[1
]}

White, T ^{[1
]}

Barr, A ^{[1
]}

Mathew, L ^{[1
]}

Huang, M ^{[1
]}

Egley, S ^{[1
]}

Zavala, M ^{[1
]}

Eades, D ^{[1
]}

Sphabmixay, K ^{[1
]}

Schaeffer, J ^{[1
]}

Triyoso, D ^{[1
]}

Rossow, M ^{[1
]}

Roan, D ^{[1
]}

Pham, D ^{[1
]}

Rai, R ^{[1
]}

Murphy, S ^{[1
]}

Nguyen, BY ^{[1
]}

White, BE ^{[1
]}

Duvallet, A ^{[1
]}

Dao, T ^{[1
]}

Mogab, J ^{[1
]}

机构：

[1] Motorola Inc, Technol Solut Org, Semicond Prod Sector, Austin, TX 78721 USA

来源：

2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2004年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we report the performance and reliability of sub-100nm TaSiN metal gate fully depleted SOI devices with high-k gate dielectric. Performance differences between fully-depleted and partially-depleted devices are highlighted. This is also the first time that an unique asymmetric degradation phenomenon between electron and hole mobility in metal/high-k devices is reported. Despite the use of high-k dielectric, we show that these devices exhibit superior reliability, noise and analog circuit performances.

引用

页码：106 / 107

页数：2

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