Package optimization of a stacked die flip chip based test package

被引:2
作者
Pohl, J [1 ]
Graml, M [1 ]
Strobel, P [1 ]
Steiner, R [1 ]
Pressel, K [1 ]
Stoeckl, S [1 ]
Offner, G [1 ]
Lee, C [1 ]
机构
[1] Infineon Technol AG, D-93049 Regensburg, Germany
来源
6TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, PROCEEDINGS (EPTC 2004) | 2004年
关键词
D O I
10.1109/EPTC.2004.1396676
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
We report a case study for the optimization of a flip chip based stacked die array test package. We demonstrate the importance of package substrate design and substrate thickness on the processibility and package warpage control. We found that for thin substrates copper balancing of the top and bottom die is crucial. We show the impact of flip chip die thickness and substrate thickness on the die attach of the top die(s) in the stack. Investigations on different top die attach alternatives show that tape die attach can have advantages. We demonstrate the importance of the vertical stack structure (i.e. flip chip thickness) and material selection (i.e. mold compound) on the overall warpage control of the package. The results show that even small changes in the package structure can have large impact on the warpage characteristics of the stacked die package.
引用
收藏
页码:590 / 594
页数:5
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