Novel dual damascene platterning technology for ultra LOW-K dielectrics

被引：4

作者：

Yeh, CN ^{[1
]}

Lu, YC ^{[1
]}

Wu, TC ^{[1
]}

Lu, HH ^{[1
]}

Chen, CC ^{[1
]}

Tao, HJ ^{[1
]}

Liang, MS ^{[1
]}

机构：

[1] TSMC, Res & Dev, Adv Module Technol Div, Hsinchu 30077, Taiwan

来源：

PROCEEDINGS OF THE IEEE 2003 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2003年

关键词：

D O I：

10.1109/IITC.2003.1219751

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this article, we present a novel via-sealing-architecture (VISA) dual damascene patterning technology, featuring with immunity from PR poisoning and ash-induced degradation of porous low-k dielectrics, and planar surface topology for both via and trench lithography. Its electrical performance is demonstrated by integrating Cu and porous organosilicate glass (OSG), kappa=2.2, with 90nm design rule and 193nm lithography on the 300mm wafer. The new architecture, which consists of depositing hard-mask dielectrics over the etched hole to form a sealed structure, enables this patterning technology extending to 65nm generation and below without influenced by low-k materials and lithography technology.

引用

页码：192 / 194

页数：3

共 5 条

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