Error control combining Hamming and product codes for energy efficient nanoscale on-chip interconnects

被引:5
作者
Fu, B. [1 ]
Ampadu, P. [1 ]
机构
[1] Univ Rochester, ECE Dept, Rochester, NY 14627 USA
基金
美国国家科学基金会;
关键词
NETWORKS; SCHEMES;
D O I
10.1049/iet-cdt.2008.0130
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The authors propose an energy efficient error control scheme that combines simple Hamming codes with powerful product codes for deeply scaled on-chip interconnects. By using Hamming codes in low-noise environments and product codes in high-noise environments, the proposed method achieves high reliability while maintaining energy efficiency; further, hardware sharing is introduced to reduce system overhead. To achieve the same reliability in noisy environments, the proposed method uses a lower swing voltage than a conventional Hamming implementation, resulting in a 30% energy reduction; an energy reduction of up to 40% is achieved compared to a multi-error correcting BCH code.
引用
收藏
页码:251 / 261
页数:11
相关论文
共 27 条
[1]  
[Anonymous], 2007, P 2 INT C NAN SEP
[2]  
*AR STAT U, PRED TECHN MOD
[3]   Error control schemes for on-chip communication links: The energy-reliability tradeoff [J].
Bertozzi, D ;
Benini, L ;
De Micheli, G .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2005, 24 (06) :818-831
[4]   The challenge of signal integrity in deep-submicrometer CMOS technology [J].
Caignet, F ;
Delmas-Bendhia, S ;
Sicard, E .
PROCEEDINGS OF THE IEEE, 2001, 89 (04) :556-573
[5]   Trends and challenges in VLSI circuit reliability [J].
Constantinescu, C .
IEEE MICRO, 2003, 23 (04) :14-19
[6]  
De Micheli G., 2006, NETWORKS CHIPS TECHN
[7]  
EJLALI A, 2007, P DES AUT TEST EUR C, P1
[8]  
FU B, 2008, VLSI DESIGN, DOI DOI 10.1155/2008/109490
[9]  
FU B, 2008, P 3 INT C NAN NAN 20, P1
[10]   Addressing signal integrity in Networks on Chip interconnects through crosstalk-aware double error correction coding [J].
Ganguly, Aralan ;
Pande, Partha Pratim ;
Belzer, Benjamin ;
Grecu, Cristian .
IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: EMERGING VLSI TECHNOLOGIES AND ARCHITECTURES, 2007, :317-+