Reconfigurable instruction set processors: A survey

被引：20

作者：

Barat, F ^{[1
]}

Lauwereins, R ^{[1
]}

机构：

[1] Katholieke Univ Leuven, Louvain, Belgium

来源：

11TH IEEE INTERNATIONAL WORKSHOP ON RAPID SYSTEM PROTOTYPING, PROCEEDINGS | 2000年

关键词：

D O I：

10.1109/IWRSP.2000.855217

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Reconfigurable instruction set processors have the capability, to adapt their instruction sets to the application being executed through a reconfiguration in their hardware. Through this adaptation, the) nr-e expected to achieve a great improvement rn performance compared to fixed instruction set processors. In this paper, we discuss the different hardware aspects that have to be considered during the design of such a reconfigurable processor. The topics discussed include the coupling of the processor and the reconfigurable logic, configuration, instruction coding and scheduling. granularity, hardware cache and reconfigurability. A classification of current reconfigurable processors is done according to the discussed topics.

引用

页码：168 / 173

页数：2

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