Embedded Analog-to-Digital Converters

被引:0
作者
Bult, Klaas [1 ]
机构
[1] Broadcom Corp, Bunnik, Netherlands
来源
2009 PROCEEDINGS OF ESSCIRC | 2009年
关键词
CMOS SUBRANGING ADC; PIPELINED ADC; BACKGROUND CALIBRATION; A/D CONVERTER; FOLDING ADC; 8-B; 5-BIT; ARRAY; 10-B;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Systems-on-Chips (So Cs) have become a reality in the past decade. Several dozens of different functional blocks are being integrated on a single die, reaching transistor counts of up to half a billion. From the Analog portion of an SoC the Data Converters are probably among the most challenging blocks, often limiting system performance and dominating power dissipation. However, requirements regarding yield, die-size, scalability, noise immunity, power and the fact that logic is almost for free, cause distinct differences between embedded Data Converters and their stand-alone, usually general purpose, counterparts. This paper describes these differences and provides an overview of the state-of-the art in Analog-to-Digital Conversion.
引用
收藏
页码:53 / 65
页数:13
相关论文
共 60 条
[51]  
Schvan Peter, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, P544, DOI 10.1109/ISSCC.2008.4523298
[52]  
SHIN S, 2008, S VLSI CIRC JUN, V22, P218
[53]   A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC [J].
Siragusa, E ;
Galton, I .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (12) :2126-2138
[54]   A 1.8-V 1.6-GSample/s 8-b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency [J].
Taft, RC ;
Menkus, CA ;
Tursi, MR ;
Hidri, O ;
Pons, V .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (12) :2107-2115
[55]   A 100-MS/s 8-b CMOS subranging ADC with sustained parametric performance from 3.8 V down to 2.2 V [J].
Taft, RC ;
Tursi, MR .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (03) :331-338
[56]  
TAFT RC, 2009, IEEE INT SOL STAT CI, V52, P78
[57]   Design techniques and implementation of an 8-bit 200-MS/s interpolating/averaging CMOS A/D converter [J].
Uyttenhove, K ;
Vandenbussche, J ;
Lauwers, E ;
Gielen, GGE ;
Steyaert, MSJ .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (03) :483-494
[58]   HIGH-SPEED 7-BIT A-D CONVERTER [J].
VANDEPLASSCHE, RJ ;
VANDERGRIFT, REJ .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1979, 14 (06) :938-943
[59]   Analog-to-digital converter survey and analysis [J].
Walden, RH .
IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, 1999, 17 (04) :539-550
[60]   A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration [J].
Wang, XY ;
Hurst, PJ ;
Lewis, SH .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (11) :1799-1808