FPGA Design & Implementation of optimized RC5 Block Cipher

被引：0
|
作者：
Acharya, Lomash Chandra [1 ]
Purohit, Jyoti Prakash [1 ]
Bairwa, Surendra Kumar [2 ]
Kumawat, Harish Chandra [1 ]
机构：
[1] Govt Engn Coll Bikaner, Dept Elect & Commun Engn, Bikaner, Rajasthan, India
[2] Govt Polytech Coll, Dept Elect Engn, Chittaurgarh, Rajasthan, India
来源：
2017 2ND INTERNATIONAL CONFERENCE ON TELECOMMUNICATION AND NETWORKS (TEL-NET) | 2017年
关键词：
RC5 Encryption algorithm; pipelining; resource sharing; Aldec Active HDL; Xilinx ISE Design Suite; Virtex-6;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Today wireless communication is the fastest growing sector for transmission of digitally stored data. In wireless communication certain security protocols are used. The security layers of these protocols requires encryption algorithm to provide transmission security. In this paper, FPGA Design and implementation of optimized RC5 block cipher has been proposed considering the various aspect such as speed, area and power. RC5 block cipher is based on RC5 encryption algorithm. The parameter of RC5 encryption algorithm taken are word (w) = 32, round(r) = 4 and key (k) = 128. The simulation is done on Aldec Active HDL. For FPGA Design various results are obtained using Xilinx ISE Design Suite 14.1. The target board is vertex-6 and FPGA device Chosen is 6v1x75tff484-3. The proposed design ensures high throughput with 6-stage pipelined architecture for r = 4.
引用
收藏
页码：360 / 365
页数：6
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