Compensation of track and hold frequency response mismatches in interleaved analog to digital converters for high-speed communications

In this paper we investigate the effect of mismatches in the frequency responses of the track-and-hold (T&H) amplifiers of an interleaved array of analog-to-digital converters (ADC) used as the front-end of a high-speed communications receiver. Furthermore, we introduce digital signal processing (DSP) techniques to compensate the performance loss caused by these mismatches. These techniques take advantage of the specific application of the ADC as a front-end of a digital communication receiver, assumed to be based on a parallel processing implementation of a decision-feedback equalizer (DFE) [1], [2]. With a relatively simple modification, the DFE can be transformed into a multiple-input, multiple-output (MIMO) equalizer. The latter effectively compensates the effect of the T&H frequency response mismatch. The performance measure used in this paper is the signal to noise ratio (SNR) at the slicer. An SNR loss of 2.5 dB or more could result from the T/H mismatch. Most of this loss is compensated by the MIMO equalizer. Our conclusions can be easily extended to receiver architectures other than the DFE, for example maximum-likelihood sequence estimation (MLSE) [3]. As an example of the effectiveness of the techniques introduced here, we present an optical receiver with electronic dispersion compensation (EDC) for the emergent IEEE 802.3aq standard for 10Gb/s Ethernet over multimode fibers [4].