A 1.2-pJ/bit 16-Gb/s 60-GHz OOK Transmitter in 65-nm CMOS for Wireless Network-On-Chip

被引:63
|
作者
Yu, Xinmin [1 ]
Sah, Suman Prasad [1 ]
Rashtian, Hooman [2 ]
Mirabbasi, Shahriar [3 ]
Pande, Partha Pratim [1 ]
Heo, Deukhyoun [1 ]
机构
[1] Washington State Univ, Sch Elect Engn & Comp Sci, Pullman, WA 99163 USA
[2] Univ Calif Davis, Dept Elect & Comp Engn, Davis, CA 95616 USA
[3] Univ British Columbia, Dept Elect & Comp Engn, Vancouver, BC V6T 1Z4, Canada
基金
美国国家科学基金会;
关键词
Bulk driven; CMOS; drive amplifier (DA); low power; millimeter wave; modulator; neutralization; on-off keying (OOK); transmitter (TX); voltage-controlled oscillator (VCO); wireless network-on-chip (WiNoC); LOW-NOISE AMPLIFIER; DESIGN;
D O I
10.1109/TMTT.2014.2347919
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a high-efficiency 60-GHz on-off keying (OOK) transmitter (TX) designed for wireless network-on-chip applications. Aiming at an intra-chip communication distance of 20 mm, the TX consists of a drive amplifier (DA), a high-speed OOK modulator, and a transformer-coupled voltage-controlled oscillator. For high efficiency, a common-source topology with a drain-to-gate neutralization technique is chosen for the DA. A detailed mathematical design methodology is derived for the neutralization technique. The bulk-driven OOK modulator employs a novel dual feedthrough cancellation technique, resulting in a 30-dB on-off ratio. Fabricated in a 65-nm bulk CMOS process, the TX consumes only 19 mW from a 1-V supply, and occupies an active area of 0.077 mm(2). A maximum modulation data rate of 16 Gb/s with 0.75-dBm output power is demonstrated through measurements, which translates to a bit-energy efficiency of 1.2 pJ/bit.
引用
收藏
页码:2357 / 2369
页数:13
相关论文
共 50 条
  • [31] A 10-Gb/s 0.71-pJ/bit Forwarded-Clock Receiver Tolerant to High-Frequency Jitter in 65-nm CMOS
    Chung, Sang-Hye
    Kim, Young-Ju
    Kim, Yong-Hun
    Kim, Lee-Sup
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2016, 63 (03) : 264 - 268
  • [32] A Fully Integrated 60 GHz 10 Gb/s QPSK Transceiver with Digital Transmitter and T/R Switch in 65nm CMOS
    Song, Zheng
    Lin, Jianfu
    Li, Yutian
    Ye, Jialiang
    Ma, Ruichang
    Chi, Baoyong
    2019 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM (RFIC), 2019, : 123 - 126
  • [33] A 16-Gb/s Low-Power Inductorless Wideband Gain-Boosted Baseband Amplifier With Skewed Differential Topology for Wireless Network-on-Chip
    Baylon, Joe
    Yu, Xinmin
    Gopal, Srinivasan
    Molavi, Reza
    Mirabbasi, Shahriar
    Pande, Partha Pratim
    Heo, Deukhyoun
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018, 26 (11) : 2406 - 2418
  • [34] A 60-GHz Energy Harvesting Module with On-chip Antenna and Switch for Co-integration with ULP Radios in 65-nm CMOS with Fully Wireless Mm-wave Power Transfer Measurement
    Gao, Hao
    Matters-Kammerer, Marion K.
    Harpe, Pieter
    Milosevic, Dusan
    van Roermund, Arthur
    Linnartz, Jean-Paul
    Baltus, Peter G. M.
    2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2014, : 1640 - 1643
  • [35] A 60-GHz 10-Gb/s OOK Modulator with Transformer-Feedback Technique for High Gain and On-Off Isolation in 90-nm CMOS
    Chuang, Po-Hsiang
    Lin, Jung-Lin
    Lin, Yu-Hsuan
    Wang, Yunshan
    Wang, Huei
    2018 ASIA-PACIFIC MICROWAVE CONFERENCE PROCEEDINGS (APMC), 2018, : 732 - 734
  • [36] A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS
    Park, Kwanseo
    Bae, Woorham
    Lee, Jinhyung
    Hwang, Jeongho
    Jeong, Deog-Kyoon
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018, 53 (10) : 2982 - 2993
  • [37] A 0.186 pJ/bit, 6-Gb/s, Energy-Efficient, Half-Rate Hybrid Circuit Topology in 1.2V, 65 nm CMOS
    Govindaswamy, Prema Kumar
    Khatun, Mursina
    Pasupureddi, Vijay Shankar
    2024 25TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, ISQED 2024, 2024,
  • [38] A 0.2 pJ/bit, Energy-Efficient, Half-Rate Hybrid Circuit Topology at 6-Gb/s in 1.2V, 65 nm CMOS
    Govindaswamy, Prema Kumar
    Khatun, Mursina
    Pasupureddi, Vijay Shankar
    2024 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS 2024, 2024,
  • [39] An Integrated 60GHz 5Gb/s QPSK Transmitter with On-Chip T/R Switch and Fully-Differential PLL Frequency Synthesizer in 65nm CMOS
    Kuang, Lixue
    Chi, Baoyong
    Chen, Lei
    Wei, Meng
    Yu, Xiaobao
    Wang, Zhihua
    PROCEEDINGS OF THE 2013 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 2013, : 413 - 416
  • [40] 60-GHz Four-Element Phased-Array Transmit/Receive System-in-Package Using Phase Compensation Techniques in 65-nm Flip-Chip CMOS Process
    Kuo, Jing-Lin
    Lu, Yi-Fong
    Huang, Ting-Yi
    Chang, Yi-Long
    Hsieh, Yi-Keng
    Peng, Pen-Jui
    Chang, I-Chih
    Tsai, Tzung-Chuen
    Kao, Kun-Yao
    Hsiung, Wei-Yuan
    Wang, James
    Hsu, Yungping Alvin
    Lin, Kun-You
    Lu, Hsin-Chia
    Lin, Yi-Cheng
    Lu, Liang-Hung
    Huang, Tian-Wei
    Wu, Ruey-Beei
    Wang, Huei
    IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2012, 60 (03) : 743 - 756