Layout optimization methodology for ring-based on-chip optical network

被引:2
|
作者
Wang, Kang [1 ]
Wang, Kun [2 ]
Yang, Yintang [3 ]
Wang, Yue [1 ]
Gu, Huaxi [1 ]
机构
[1] Xidian Univ, Sch Telecommun Engn, Xian 710071, Shaanxi, Peoples R China
[2] Xidian Univ, Sch Comp Sci & Technol, Xian 710071, Shaanxi, Peoples R China
[3] Xidian Univ, Sch Microelect, Xian 710071, Shaanxi, Peoples R China
来源
IEICE ELECTRONICS EXPRESS | 2019年 / 16卷 / 20期
基金
美国国家科学基金会;
关键词
optical; on-chip network; interconnect; layout optimization; ARCHITECTURE;
D O I
10.1587/elex.16.20190458
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
When integrating an optical network into a chip, the communication characteristics and the power cost of the network should be considered. In this letter, to fulfill data coherence communication, a non-intention ring-based optical network which supports multicast and broadcast is studied. To further eliminate the power penalty cost due to waveguide crossing, a layout optimization methodology is proposed. By dividing an optical network into several sections and placing them partby-part into different areas, the total number of cross points is reduced by 83.3%, 71.7% and 70.2% in networks supporting four-, six- and eight-core communication respectively.
引用
收藏
页码:1 / 6
页数:6
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