Superior Cu Fill with Highly Reliable Cu/ULK Integration for 10nm Node and Beyond

被引：0

作者：

Matsuda, T. ^{[1
]}

Lee, J. J. ^{[1
]}

Han, K. H. ^{[1
]}

Park, K. H. ^{[1
]}

Cha, J. O. ^{[1
]}

Baek, J. M. ^{[1
]}

Yim, T. J. ^{[1
]}

Kim, D. C. ^{[1
]}

Lee, D. H. ^{[1
]}

Kim, J. N. ^{[1
]}

Choi, S. H. ^{[1
]}

Lee, E. B. ^{[1
]}

Nam, S. D. ^{[1
]}

Lee, H. B. ^{[1
]}

Cho, Y. W. ^{[1
]}

Kim, I. S. ^{[1
]}

Kwon, B. H. ^{[1
]}

Ahn, S. H. ^{[1
]}

Yun, J. H. ^{[1
]}

Kim, B. H. ^{[1
]}

Yoon, B. U. ^{[1
]}

Hong, J. S. ^{[1
]}

Lee, N. I. ^{[1
]}

Choi, S. ^{[1
]}

Kang, H. K. ^{[1
]}

Chung, E. S. ^{[1
]}

机构：

[1] Samsung Elect Co Ltd, Hwasung City 445701, Gyeonggi Do, South Korea

来源：

2013 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2013年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

It is possible to overcome Cu void issues beyond 10nm node device by adapting CVD-Ru liner instead of conventional PVD Ta liner. However, CVD Ru liner integration degrades TDDB performance without optimizing its scheme. In this paper, superior gap-fill performance without TDDB performance degradation will be described in our optimized integration scheme along with a proposal for the mechanism of TDDB degradation in the Ru integration scheme. CVD-Ru liner is the prime candidate for Cu metallization at 10nm node and beyond.

引用

页数：4

共 8 条

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Miyazakib, Tadakazu
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