Enhancing power cycling capability of power semiconductor devices is highly demanded in order to increase the long-term reliability of multilevel inverters. Ageing of power switches and their cooling systems leads to their accelerated damage due to excess power losses and junction temperatures. Therefore, thermal stresses relief (TSR) is the most effective solution for lifetime extension of power semiconductor devices. This paper presents a new TSR carrier-based pulse width modulation (TSRPWM) strategy for extending the lifetime of semiconductor switches in single-phase multilevel inverters. The proposed strategy benefits the inherent redundancy among switching states in multilevel inverters to optimally relieve the thermally stressed device. The proposed algorithm maintains the inverter operation without increased stresses on healthy switches and without reduction of the output power ratings. In addition, the proposed algorithm preserves voltage balance of the dc-link capacitors. The proposed strategy is validated on a single-phase five-level T-type inverter system with considering different locations of thermal stresses detection. Experimental prototype of the selected case study is built to verify the results. Moreover, comparisons with the most featured strategies in literature are given in detail.
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页码:9376 / 9388
页数:13
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Aly M., 2015, 2015 IEEE International Telecommunications Energy Conference (INTELEC), P1
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Univ Grenoble, Grenoble Elect Engn Lab, F-38402 St Martin Dheres, FranceUniv Grenoble, Grenoble Elect Engn Lab, F-38402 St Martin Dheres, France
Avenas, Yvan
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Dupont, Laurent
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French Inst Sci & Technol Transport Dev & Network, Lab New Technol, F-78000 Versailles, FranceUniv Grenoble, Grenoble Elect Engn Lab, F-38402 St Martin Dheres, France
Dupont, Laurent
;
Khatir, Zoubir
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French Inst Sci & Technol Transport Dev & Network, Lab New Technol, F-78000 Versailles, FranceUniv Grenoble, Grenoble Elect Engn Lab, F-38402 St Martin Dheres, France
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Univ Minnesota, Dept Elect Engn, 200 Union St SE, Minneapolis, MN 55455 USAUniv Minnesota, Dept Elect Engn, 200 Union St SE, Minneapolis, MN 55455 USA
Baranwal, Rohit
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Basu, Kaushik
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DynaPower, Burlington, VT 05401 USAUniv Minnesota, Dept Elect Engn, 200 Union St SE, Minneapolis, MN 55455 USA
Basu, Kaushik
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Mohan, Ned
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Univ Minnesota, Dept Elect Engn, 200 Union St SE, Minneapolis, MN 55455 USAUniv Minnesota, Dept Elect Engn, 200 Union St SE, Minneapolis, MN 55455 USA
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Univ Grenoble, Grenoble Elect Engn Lab, F-38402 St Martin Dheres, FranceUniv Grenoble, Grenoble Elect Engn Lab, F-38402 St Martin Dheres, France
Avenas, Yvan
;
Dupont, Laurent
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机构:
French Inst Sci & Technol Transport Dev & Network, Lab New Technol, F-78000 Versailles, FranceUniv Grenoble, Grenoble Elect Engn Lab, F-38402 St Martin Dheres, France
Dupont, Laurent
;
Khatir, Zoubir
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French Inst Sci & Technol Transport Dev & Network, Lab New Technol, F-78000 Versailles, FranceUniv Grenoble, Grenoble Elect Engn Lab, F-38402 St Martin Dheres, France
机构:
Univ Minnesota, Dept Elect Engn, 200 Union St SE, Minneapolis, MN 55455 USAUniv Minnesota, Dept Elect Engn, 200 Union St SE, Minneapolis, MN 55455 USA
Baranwal, Rohit
;
Basu, Kaushik
论文数: 0引用数: 0
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DynaPower, Burlington, VT 05401 USAUniv Minnesota, Dept Elect Engn, 200 Union St SE, Minneapolis, MN 55455 USA
Basu, Kaushik
;
Mohan, Ned
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Univ Minnesota, Dept Elect Engn, 200 Union St SE, Minneapolis, MN 55455 USAUniv Minnesota, Dept Elect Engn, 200 Union St SE, Minneapolis, MN 55455 USA