Variation in process conditions of porogen-based low-k films: A method to improve performance without changing existing process steps in a sub-100 nm Cu damascene integration route

被引：0

作者：

De Roest, D. ^{[1
]}

Travaly, Y. ^{[2
]}

Beynet, J. ^{[1
]}

Sprey, H. ^{[1
]}

Labat, J. ^{[2
]}

Huffman, C. ^{[2
]}

Verdonck, P. ^{[2
]}

Kaneko, S. ^{[3
]}

Matsushita, K. ^{[3
]}

Kobayashi, N. ^{[3
]}

Beyer, G. ^{[2
]}

机构：

[1] ASM Belgium, B-3001 Louvain, Belgium

[2] IMEC, B-3001 Louvain, Belgium

[3] ASM Japan, Tokyo, Japan

来源：

MICROELECTRONIC ENGINEERING | 2010年 / 87卷 / 03期

关键词：

Low-k; Porogen; Cure time; Process variation; Anneal; Capping layer;

D O I：

10.1016/j.mee.2009.06.036

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This article describes less explored solutions to improve interconnect performance without changing established steps (etch, strip, clean, CMP) in a sub-100 nm integration route. Process conditions of the porogen-based low-k are adjusted by (1) varying the curing time (2) adding a thermal anneal step prior to CuO reduction or (3) depositing a capping layer on top of the low-k after curing. The low-k material examined in this study is Aurora (R) ELK HM (k similar to 2.5). The integration process was robust against these variations, showing good electrical yield for all process splits. RC-product was improved when using a shorter curing time and when an anneal step prior to CuO reduction was performed. The use of a thicker capping layer decreased capacitance, showing an improved protection against damage. (C) 2009 Elsevier B.V. All rights reserved.

引用

页码：311 / 315

页数：5