DESIGN AND IMPLEMENTATION OF LINEAR PRECODING LTE DOWNLINK BASED ON FPGA

被引:0
作者
Chaeriyah, Nur [1 ]
Astuti, Rina Pudji [1 ]
Darlis, Denny [1 ]
机构
[1] Telkom Univ, Sch Engn, Bandung, Indonesia
来源
2013 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATION, NETWORKS AND SATELLITE (COMNETSAT) | 2013年
关键词
Linear precoding; codebook; FPGA; VHDL; MIMO;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The problem that often occur in multi-antenna wireless communication is how to maximize the throughput. Precoding is a generalization of beamforming to support multi-layer transmission in multi-antenna wireless communications. Beamforming is a signal processing technique used in sensor arrays for directional signal transmission or reception. In conventional single-layer beamforming, the same signal is emitted from each of the transmit antennas with appropriate weighting such that the signal power is maximized at the receiver output. When the receiver has multiple antennas, single-layer beamforming cannot simultaneously maximize the signal level at all of the receive antennas. Thus, in order to maximize throughput in a receiving antenna system, integrated precoding in multi-layer beamforming is required. LTE linear precoding system for the transmitter side is built in this research. The precoding system will be built in VHDL code and will be implemented on FPGA. In this research, the precoding sistem consists of 64-QAM Mapper as input system, and will be connected to OFDM (IFFT) block. The precoding is built based on Transmission Mode (TM) 6 of LTE release 9 and will be using 3GPP codebook standard as the precoding matrix for TM 6 for 2x2 MIMO. [GRAPHICS] The research shows that by the used of linear precoding system in transmission, it decreases the complexion of detection system in precoding block on the receiver side. The implementation process shows that the research is implementable on hardware and will use 62% occupied slices, 11% slice register, and 27% of bounded IOBs resources of FPGA. with 2021 clock in total process, 121 clock in delay process and 1900 clocks to produce one OFDM symbol. The bitrate of the system is 161.68 Mbps.
引用
收藏
页码:50 / 54
页数:5
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