240nm pitch 4GDRAM array MOSFET technologies with x-ray lithography

This paper describes 240nm pitch array MOSFET technologies which realize 0.1152 mu m(2) cell size for 4GDRAM. Main features of the array MOSFET are (1)120nm line and spaces(L/S) Gate, (2) L/S isolation, (3)Self Aligned Contact (SAC) at 120nm wide gate-gate space, and (4)40nm shallow junction under the SAC plug. X-ray lithography is used for ultra fine patterning and 200nm pitch(100nm L/S) active area array is demonstrated. A 120nm isolation is realized using shallow trench isolation(STI) whose depth is 200nm. In-situ phosphorus(P) doped poly-silicon is used for SAC plug to make a contact at 120nm gate space. The shallow junction of 40nm depth, which suppresses Vth roll-off, is formed by P diffusion from the plug. These technologies can achieve cell area of 0.1152 mu m(2)(8F(2)), for 4GDRAM.