Ultimately thin double-gate SOI MOSFETs

被引:177
|
作者
Ernst, T [1 ]
Cristoloveanu, S
Ghibaudo, G
Ouisse, T
Horiguchi, S
Ono, Y
Takahashi, Y
Murase, K
机构
[1] UJF, UMR CNRS, INPG, Inst Microelect Electromagnetism & Photon, F-38016 Grenoble 1, France
[2] NTT Corp, Basic Res Labs, Kanagawa 2430198, Japan
关键词
double gate; mobility; MOS transistor; MOSFET; SOI; thin film;
D O I
10.1109/TED.2003.811371
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The operation of 1-3 nm thick SOI MOSFETs, in double-gate (PG) mode and single-gate (SG) mode (for either front or back channel), is systematically analyzed. Strong interface coupling and threshold voltage variation, large influence of substrate depletion underneath the buried oxide, absence of drain current transients, degradation in electron mobility are typical effects in these ultra-thin MOSFETs. The comparison of SG and DG configurations demonstrates the superiority of DG-MOSFETs: ideal subthreshold swing and remarkably improved transconductance (consistently higher than twice the value in SG-MOSFETs). The experimental data and the difference between SG and DG modes is explained by combining classical models with quantum calculations. The key effect in ultimately thin DG-MOSFETs is volume inversion, which primarily leads to an Improvement in mobility, whereas the total inversion charge is only marginally modified.
引用
收藏
页码:830 / 838
页数:9
相关论文
共 50 条
  • [1] Characterization of ultra-thin SOI films for double-gate MOSFETs
    Allibert, F
    Vinet, M
    Lolivier, J
    Deleonibus, S
    Cristoloveanu, S
    2002 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2002, : 187 - 188
  • [2] SCALING THEORY FOR DOUBLE-GATE SOI MOSFETS
    SUZUKI, K
    TANAKA, T
    TOSAKA, Y
    HORIE, H
    ARIMOTO, Y
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1993, 40 (12) : 2326 - 2329
  • [3] Hall effect measurements in double-gate SOI MOSFETs
    Vandooren, A
    Cristoloveanu, S
    Flandre, D
    Colinge, JP
    SOLID-STATE ELECTRONICS, 2001, 45 (10) : 1793 - 1798
  • [4] ANALYTICAL MODELS FOR N(+)-P(+) DOUBLE-GATE SOI MOSFETS
    SUZUKI, K
    SUGII, T
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1995, 42 (11) : 1940 - 1948
  • [5] A simple modelling of device speed in double-gate SOI MOSFETs
    Rajendran, K
    Samudra, G
    MICROELECTRONICS JOURNAL, 2000, 31 (04) : 255 - 259
  • [6] Mobility issues in double-gate SOI MOSFETs: Characterization and analysis
    Rodriguez, N.
    Cristoloveanu, S.
    Nguyen, L. Pham
    Garniz, F.
    ESSDERC 2007: PROCEEDINGS OF THE 37TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2007, : 271 - +
  • [7] ANALYTICAL SURFACE-POTENTIAL EXPRESSION FOR THIN-FILM DOUBLE-GATE SOI MOSFETS
    SUZUKI, K
    TANAKA, T
    TOSAKA, Y
    HORIE, H
    ARIMOTO, Y
    ITOH, T
    SOLID-STATE ELECTRONICS, 1994, 37 (02) : 327 - 332
  • [8] Impact of asymmetric channel configuration on the linearity of double-gate SOI MOSFETs
    Pavanello, Marcelo Antonio
    Cerdeira, Antonio
    Martino, Joao Antonio
    Raskin, Jean-Pierre
    Flandre, Denis
    PROCEEDINGS OF THE 6TH INTERNATIONAL CARIBBEAN CONFERENCE ON DEVICES, CIRCUITS, AND SYSTEMS, 2006, : 187 - +
  • [9] A review of core compact models for undoped double-gate SOI MOSFETs
    Ortiz-Conde, Adelmo
    Garcia-Sanchez, Francisco J.
    Muci, Juan
    Malobabic, Slavica
    Liou, Juin J.
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (01) : 131 - 140
  • [10] Mobility enhancement in (110)-oriented ultra-thin-body single-gate and double-gate SOI MOSFETs
    Hiramoto, Toshiro
    Tsutsui, Gen
    Saitoh, Masurni
    Nagumo, Toshiharu
    Saraya, Takuya
    2006 INTERNATIONAL WORKSHOP ON NANO CMOS, PROCEEDINGS, 2006, : 44 - 55