Bandpass sigma-delta modulator employing SAW resonator as loop filter

被引:11
作者
Yu, Rui [1 ]
Xu, Yong Ping [1 ]
机构
[1] Natl Univ Singapore, Dept Elect & Comp Engn, Singapore 117576, Singapore
关键词
analog-to-digital converter (ADC); sigma-delta modulator (Sigma Delta M); bandpass (BP); surface acoustic wave (SAW) resonator; RECEIVER;
D O I
10.1109/TCSI.2007.890615
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Continuous-time bandpass (BP) sigma-delta modulators (Sigma Delta Ms) employing surface acoustic wave (SAW) resonators as loop filters are presented. Compared with the loop filters realized with G(m)-C and LC resonators, the SAW resonator has the advantage of high-Q factor, wide resonant frequency range and accurate resonant frequency without the need for automatic tuning. With the proposed anti-resonance cancellation and loop filter phase compensation techniques, a second- and a fourth-order BP Sigma Delta Ms are demonstrated in a 0.35-mu m CMOS technology. Both modulators are tested with 47.3-MHz off-chip SAW resonators. The second-order modulator attains a dynamic range of 57 dB and peak signal-to-noise distortion ratio (SNDR) of 54 dB and the fourth-order one achieves a dynamic range of 69 dB and peak SNDR of 66 dB, both in a 200-kHz signal bandwidth. The fourth-order modulator is also measured in a 3.84-MHz signal bandwidth and achieves a dynamic range of 52.5 dB and peak SNDR of 50 dB, an effective 8-bit resolution.
引用
收藏
页码:723 / 735
页数:13
相关论文
共 28 条
[1]   A 160-MHz fourth-order double-sampled SC bandpass sigma-delta modulator [J].
Bazarjani, S ;
Snelgrove, WM .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1998, 45 (05) :547-555
[2]  
Cherry J., 2000, CONTINUOUS TIME DELT
[3]   3.3-V 240-MS/s CMOS bandpass ΣΔ modulator using a fast-settling double-sampling SC filter [J].
Cheung, VSL ;
Luong, HC .
2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2004, :84-87
[4]   A 1-V 10.7-MHz switched-opamp, bandpass ΣΔ modulator using double-sampling finite-gain-compensation technique [J].
Cheung, VSL ;
Luong, HC ;
Ki, WH .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2002, 37 (10) :1215-1225
[5]   IF-sampling fourth-order bandpass ΔΣ modulator for digital receiver applications [J].
Cosand, AE ;
Jensen, JF ;
Choe, HC ;
Fields, CH .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (10) :1633-1639
[6]   A 3.3-V CMOS 10.7-MHz sixth-order bandpass ΣΔ modulator with 74-dB dynamic range [J].
Cusinato, P ;
Tonietto, D ;
Stefani, F ;
Baschirotto, A .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (04) :629-638
[7]   A 30-mW 10.7-MHz pseudo-N-path sigma-delta band-pass modulator [J].
Francesconi, F ;
Caiulo, G ;
Liberali, V ;
Maloberti, F .
1996 SYMPOSIUM ON VLSI CIRCUITS - DIGEST OF TECHNICAL PAPERS, 1996, :60-61
[8]  
GAO W, 1998, S VLSI CIRC, P174
[9]   A 950-MHz IF second-order integrated LC bandpass delta-sigma modulator [J].
Gao, WN ;
Snelgrove, WM .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (05) :723-732
[10]   A TRANSFORMATION FOR DIGITAL-SIMULATION OF ANALOG FILTERS [J].
GARDNER, FM .
IEEE TRANSACTIONS ON COMMUNICATIONS, 1986, 34 (07) :676-680