The successive over-relaxation method in reconfigurable hardware

被引：0

作者：

Kasbah, Safaa J. ^{[1
]}

Haraty, Ramzi A. ^{[1
]}

Damaj, Issarn W. ^{[2
]}

机构：

[1] Lebanese Amer Univ, Div Comp Sci & Math, Beirut, Lebanon

[2] Dhofar Univ, Dept Elect & Comp Engn, Salalah, Oman

来源：

IMECS 2007: INTERNATIONAL MULTICONFERENCE OF ENGINEERS AND COMPUTER SCIENTISTS, VOLS I AND II | 2007年

关键词：

hardware design; high performance computing; iterative methods; parallelization;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper presents the first hardware implementation of the Successive Over-Relaxation (SOR) method for the solution of a 2D Poisson equation. We use Handel-C, a high level language for the implementation of algorithms on hardware, to code and implement our design which we map onto high-performance Field Programmable Gate Arrays (FPGAs), such as, Virtex II Pro, Altera Stratix, and Spartan3L. We use the FPGA vendors' proprietary software to analyze the design implementation performance. Besides, we implement SOR using C++ and compare our timing results with the obtained C++ version results. Our findings prove that SOR in hardware outperforms SOR in software.

引用

页码：2395 / +

页数：2

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