Special Session: Delay Fault Testing - Present and Future

被引：5
作者：
Mahmod, Jubayer [1 ]
Millican, Spencer [1 ]
Guin, Ujjwal [1 ]
Agrawal, Vishwani [1 ]
机构：
[1] Auburn Univ, Dept Elect & Comp Engn, Auburn, AL 36849 USA
来源：
2019 IEEE 37TH VLSI TEST SYMPOSIUM (VTS) | 2019年
关键词：
Survey; delay fault testing; static timing analysis; small delay defect; hardware Trojan; recycled IC; timing-aware ATPG; TEST PATTERN GENERATION; COUNTERFEIT INTEGRATED-CIRCUITS; QUALITY; ATPG; SIMULATION; COVERAGE; DESIGN; COMPACTION; ALGORITHM; MODEL;
D O I：
10.1109/vts.2019.8758662
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This article presents a brief survey of digital delay fault testing, which lists 100+ references on fault models, simulators, ATPG, DFT, and tools. Continuing studies are needed in this maturing field for new technologies, signal integrity, process variations, faster than critical path operation, asynchronous circuits, counterfeit ICs, and hardware Trojans. This information is compiled to provide direction to students, practicing engineers, and researchers alike.
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页数：10
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