On the asymmetry of the DC and low-frequency noise characteristics of vertical nanowire MOSFETs with bulk source contact

被引：0
作者：
Simoen, Eddy [1 ]
Veloso, Anabela [1 ]
Matagne, Philippe [1 ]
机构：
[1] UPM, IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
来源：
SOLID-STATE ELECTRONICS | 2022年 / 191卷
关键词：
Vertical nanowires; Gate-all-around; Low-frequency noise; Forward and reverse operation; JUNCTIONLESS;
D O I：
10.1016/j.sse.2022.108268
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this work, the impact of switching the source and drain on the low-frequency noise of Gate-All-Around (GAA) Vertical Nanowire (VNW) n-and pMOSFETs fabricated on bulk silicon wafers is investigated. Switching the role of the electrodes results in an increase in the absolute value of the threshold voltage, a higher subthreshold slope and maximum transconductance. For the p-channel devices, significantly lower 1/f noise is observed in reverse operation compared with the normal forward configuration. Considering the mobility fluctuations origin of the 1/f noise, this indicates a pronounced impact of the choice of the source/drain contact on the conduction in the p-type silicon nanowires. On the other hand, little effect on the noise behaviour has been found from the in-situ boron doping density in the NWs. For the n-channel FETs, qualitatively similar results have been obtained with respect to the 1/f noise PSD. At the same time, the dominant flicker noise mechanism changes from Ag domi-nated in F operation to rather delta n in R mode.
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页数：6
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