A Fast Automatic Frequency Calibration (AFC) Scheme for Phase-Locked Loop (PLL) Frequency Synthesizer

被引：0

作者：

Jeong, Chan-Young ^{[1
]}

Choi, Dong-Ho ^{[1
]}

Yoo, Changsik ^{[1
]}

机构：

[1] Hanyang Univ, Dept ECE, Integrated Circuit Lab, Seoul 133791, South Korea

来源：

RFIC: 2009 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM | 2009年

关键词：

Automatic frequency calibration (AFC); voltage controlled oscillator (VCO); phase locked loop (PLL); frequency synthesizer; phase noise; VCO;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A noble automatic frequency calibration (AFC) scheme is proposed for phase-locked loop (PILL) based frequency synthesizer. For fast AFC operation, the frequency control code is updated right after the frequency difference is detected. The uncertainty of the phase relationship between the reference clock and VCO output is eliminated by comparing the divided VCO clock with two-phase reference clocks. The AFC is applied to a CMOS frequency synthesizer. The measured worst case AFC time is less than 1.6 mu s. The AFC circuit implemented in a 0.18 mu m CMOS process occupies 0.01mm(2). The phase noise of the frequency synthesizer output is -113dBc/Hz at MHz offset from the 4GHz carrier. The whole frequency synthesizer consumes 23mW from a 1.8V supply.

引用

页码：527 / 530

页数：4

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