Fast Current Control Without Computational Delay by Minimizing Update Latency

This letter proposes a fast current control scheme for ac drives by minimizing the latency from current sampling to the updation of a pulsewidth-modulation (PWM) command. By reconstructing the architecture of a linear controller, the minimal necessary steps to obtain the output voltage are deduced as the primary calculation, and the other computation work of the current loop is done in the postcalculation after updating the PWM command. With the proposed method, the computational delay is reduced with negligible loss in the available modulation index, and a higher stability margin or system bandwidth is realized. Also, the developed controller structure exhibits inherited antiwindup characteristics. The technique has been validated by experimental investigations on a permanent magnet synchronous motor.