A Dynamic Priority Arbiter for Network-on-Chip

被引:14
作者
Wang, Jian [1 ]
Li, Yubai [1 ]
Peng, Qicong [1 ]
Tan, Taiqiu [1 ]
机构
[1] Univ Sci & Technol China, DSP Lab, Sch Commun & Informat Engn, Hefei, Peoples R China
来源
2009 IEEE INTERNATIONAL SYMPOSIUM ON INDUSTRIAL EMBEDDED SYSTEMS | 2009年
关键词
Network-on-Chip; Arbiter; network performance; buffer resource;
D O I
10.1109/SIES.2009.5196222
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
For some customized Network-on-Chip, the communication requirements among IP cores are usually non-uniform, which make the loads of input ports in one router are not balance. In order to improve the performance of Network-on-Chip, we proposed a dynamic priority arbiter. The arbiter detect the loads of input ports in every clock cycle and adjust the priority of each input port dynamically, then authorize one input ports to transfer data based on lottery mechanism. Under the uniform traffic mode in Network-on-Chip and non-uniform traffic mode such as an application of NIPEG4 decoder in Network-on-Chip, we compared the performance between Network-on-Chip based on Round-Robin arbiter and Network-on-Chip based on dynamic priority arbiter proposed in this paper. The result shows: under non-uniform traffic mode, the dynamic priority arbiter can improve the communication performance of Network-on-Chip and reduce the requirement of buffer resource in network interface.
引用
收藏
页码:253 / 256
页数:4
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