Power-aware automated pipelining of combinational circuits

Pipelining of combinational circuits with power, area and clock frequency constraints is a very useful way to increase operational speed of circuits. In this paper we formulate this problem as a Mixed Integer Non Linear Programming (MINLP) problem and we provide two heuristic methods to obtain good solutions. The first method is sensitivity based approach which gives good solution to circuits with large number of gates. The second method uses geometric programming method which is slower on large circuits, but works well for smaller designs. The two algorithms are tested on ISCAS-85 benchmark and circuits generated by our tool and compared for speed and efficiency. We have also studied impact of supply and threshold voltage variation on pipelining efficiency in terms of latency and total power consumption. Our experimental observations show the existence of a minimum power supply voltage and a threshold voltage at which the circuits generated have less latency and power consumption.