Low-power 4-way associative cache for embedded SOC design

This paper describes the details of the architecture and the operation scheme of the low power 4-way associative cache developed for the ARM9TDMI based cached-core used in the embedded SOC products. Specifically, we show 1) the reason why we select I-way for low power, 2) the problems of the conventional I-way tag in power consumption point of view, and 3) propose a new tag architecture solving those problems. In addition, we propose a new rag operation technique called tag-skipping that reduces the number of unnecessary tag look-ups thence the corresponding power) significantly with showing what the unnecessary tag look-ups are in the conventional tag operation. Experimental results validating the proposed architecture and the operation scheme are also included.