An Efficient Hardware Architecture for Stereo Disparity Estimation

被引：0

作者：

Joseph, Fradaric ^{[1
]}

Francis, Kiran ^{[1
]}

Hore, Archita ^{[1
]}

Roy, Siddhanta ^{[1
]}

Josephine, S. ^{[1
]}

Paily, Roy P. ^{[1
]}

机构：

[1] IIT Guwahati, Dept EEE, Gauhati, India

来源：

18TH INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AND TEST | 2014年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper presents an architecture for disparity estimation in real time which is designed to be used in a blind navigation assistance system. A highly pipelined hardware prototype has been designed and verified. Sum of Absolute Difference (SAD) algorithm is chosen as the cost function in the proposed architecture. The major design consideration is efficient hardware utilization and high throughput. This system is designed to support video resolutions upto 2048 x 2048 at high frame rates. The performance evaluation shows very low latency even at low processing frequency.

引用

页数：6

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