A low-power clock generator for system-on-a-chip (SoC) processors

被引：3

作者：

Fahim, AM ^{[1
]}

机构：

[1] Qualcomm Inc, San Diego, CA 92121 USA

来源：

ESSCIRC 2004: PROCEEDINGS OF THE 30TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2004年

关键词：

D O I：

10.1109/ESSCIR.2004.1356701

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a low-power, low-jitter clock generator for system-on-a-chip (SoC) processors. Low-jitter is achieved by using a ROM-less direct digital synthesizer with analog phase interpolation. Low-power is achieved by using differential and feedback replica bias circuit topologies. A 6-bit resolution prototype is implemented in 0.25um CMOS technology. Results demonstrate that the clock generator's area is 0.12 mm(2) and consumes only 1.5mA of current consumption at 2.5V. In comparison with other similar state-of-the-art implementations, this represents savings of 37.5x and 5.87x in area and power consumption, respectively.

引用

页码：395 / 398

页数：4

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