A Depth-Five Lower Bound for Iterated Matrix Multiplication

被引:5
作者
Bera, Suman K. [1 ]
Chakrabarti, Amit [1 ]
机构
[1] Dartmouth Coll, Dept Comp Sci, Hanover, NH 03755 USA
来源
30TH CONFERENCE ON COMPUTATIONAL COMPLEXITY (CCC 2015) | 2015年 / 33卷
关键词
arithmetic circuits; iterated matrix multiplication; depth five circuits; lower bound; ARITHMETIC CIRCUITS; CHASM;
D O I
10.4230/LIPIcs.CCC.2015.183
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
We prove that certain instances of the iterated matrix multiplication (IMM) family of polynomials with N variables and degree n require N-Omega(root n) gates when expressed as a homogeneous depth-five Sigma Pi Sigma Pi Sigma arithmetic circuit with the bottom fan-in bounded by N1/2-epsilon. By a depth-reduction result of Tavenas, this size lower bound is optimal and can be achieved by the weaker class of homogeneous depth-four Sigma Pi Sigma Pi circuits. Our result extends a recent result of Kumar and Saraf, who gave the same N-Omega(root n) lower bound for homogeneous depth-four Sigma Pi Sigma Pi circuits computing IMM. It is analogous to a recent result of Kayal and Saha, who gave the same lower bound for homogeneous Sigma Pi Sigma Pi Sigma circuits (over characteristic zero) with bottom fan-in at most N1-epsilon, for the harder problem of computing certain polynomials defined by Nisan-Wigderson designs.
引用
收藏
页码:183 / 197
页数:15
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