CNTFET-Based Design of Ternary Arithmetic Modules

Multiple-valued logic such as ternary logic has attracted the digital system designers attention in recent years as it offers the benefits of reduced interconnects, higher operating speeds and smaller chip area. A goal of multi-threshold circuit design could be easily achieved by incorporating the scalable threshold voltage values of carbon nanotube field effect transistors (CNTFETs). This paper proposes a novel design of low-power and high-performance ternary adder and subtractor circuit design by combining the futuristic ternary and conventional binary logic design approaches. The simplified design of ternary to a binary decoder based on negative ternary inverter and positive ternary inverter outputs, and further transmission gate-based ternary multiplexer implementation facilitates the low power consumption and energy efficiency in the implementation of the complex arithmetic circuits. Extensive HSPICE simulations are conducted with the standard 32 nm CNTFET technology in order to evaluate the performance metrics of the realized circuits. According to the simulation results, proposed ternary adder and subtractor cells show the significant improvement in energy consumption (PDP) as compared to their counterparts under different test conditions. Moreover, the ripple adder structure is realized using the proposed adder circuit in order to test the practicability of given circuits in cascaded structures.