Layout driven FPGA packing algorithm for performance optimization

被引：2

作者：

Mo, Linfeng ^{[1
]}

Wu, Chang ^{[1
]}

He, Lei ^{[1
,2
]}

Chen, Gengsheng ^{[1
]}

机构：

[1] Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China

[2] Univ Calif Los Angeles, Elect Engn Dept, Los Angeles, CA 90024 USA

来源：

IEICE ELECTRONICS EXPRESS | 2017年 / 14卷 / 11期

关键词：

FPGA; packing; placement; layout;

D O I：

10.1587/elex.14.20170419

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

FPGA is a 2D array of configurable logic blocks. Packing is to pack logic elements into device specific configurable logic blocks for subsequent placement. The traditional fixed delay model of inter and intra cluster delays used in packing does not represent post-placement delays and often leads to sub-optimal solutions. This paper presents a new layout driven packing algorithm, named LDPack, based on a novel pre-packing placement for performance optimization. Our results show that after placement and routing LDPack outperforms Xilinx ISE MAP with 8% reduction in area and 5.22% smaller critical path delay, at the cost of 18% more runtime in average.

引用

页数：10

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